--- ecos-2.0/packages/hal/i386/arch/v2_0/include/arch.inc 2002-05-24 01:03:02.000000000 +0200 +++ ecos-2.0-rdc/packages/hal/i386/arch/v2_0/include/arch.inc 2005-10-04 01:59:03.000000000 +0200 @@ -688,7 +688,7 @@ #ifndef CYGPKG_HAL_I386_MEMC_DEFINED .macro hal_memc_init - hal_a20_enable + hal_a20_enable .endm #endif --- ecos-2.0/packages/hal/i386/arch/v2_0/cdl/hal_i386.cdl 2008-02-16 16:20:22.000000000 +0100 +++ ecos-2.0-rdc/packages/hal/i386/arch/v2_0/cdl/hal_i386.cdl 2006-03-14 19:45:36.000000000 +0100 @@ -174,7 +174,20 @@ RedBoots CDL." compile -library=libextras.a redboot_linux_exec.c } - + + + cdl_component CYGPKG_REDBOOT_I386_LINUX_FLASH { + display "Provide the NOR_SPI flash upgrade in RedBoot" + flavor bool + default_value 1 + parent CYGPKG_REDBOOT_I386_OPTIONS + # active_if CYGBLD_BUILD_REDBOOT_WITH_FLASH + description "NOR_SPI flash upgrade support" + + + compile -library=libextras.a redboot_flash.c + } + } cdl_option CYGBLD_LINKER_SCRIPT { --- ecos-2.0/packages/hal/i386/arch/v2_0/src/redboot_flash.c 1970-01-01 01:00:00.000000000 +0100 +++ ecos-2.0-rdc/packages/hal/i386/arch/v2_0/src/redboot_flash.c 2006-08-05 16:14:29.000000000 +0200 @@ -0,0 +1,1174 @@ +#include +#include +#include +#include +#include +#include + +#define U32 (unsigned long) +#define S16 (short) +#define U16 (unsigned short) +#define U8 (unsigned char) + +#define TOGGLE_STATUS 0x4040 +#define READ_MODE 0xF0F0 +#define TIMEOUT_STATUS 0x2020 + +#define DELAY(I) { int i=I; while(--i);} + +static struct flash_info { + unsigned short device_id; + unsigned long flash_base; + unsigned long flash_size; + unsigned int uniform; //bottom or top flash is 0 + unsigned int num_sector; //total num of sectors + unsigned int border; //the last num of sector in first sector group + unsigned char ERASE_SERIES ; //0:AMD sequence + unsigned char WRITE_SERIES ; //0:AMD sequence + unsigned long sector0_size; //the sector size of the first sector group + unsigned long sector1_size; //the sector size of the second sector group + //SPI + unsigned long block_size; + unsigned char cmd_erase; + unsigned char cmd_write; + unsigned char dummy0; + unsigned char dummy1; + unsigned char dummy2; +}; + +static struct flash_dev { + struct flash_info *R; + unsigned long flash_base; + unsigned long block_size; + unsigned char cmd_erase; + unsigned char cmd_write; + unsigned char data_width; + int (*erase_seq)(unsigned long); + int (*write_seq)(unsigned long,unsigned short); + int (*erase)(int sector); + int (*write)(unsigned long ,unsigned long ,short, unsigned long len); +}; + +static struct flash_info NOR_FLASH_TYPE[]= +{ +#if defined(FLASH_SIZE_4M) +//MX ID ,Flash base,Flash size ,uniform,total sectors,border, , ,sector0 size,sector1 size, + {0x22A7,0xFFC00000,0x400000 ,0 ,71 ,62 ,0,0,64*1024 ,8*1024 ,0,0,0,0,0,0}, +#elif defined(FLASH_SIZE_8M) + {0x22C9,0xFF800000,0x800000 ,0 ,135 ,126 ,0,0,64*1024 ,8*1024 ,0,0,0,0,0,0}, +#endif +//MX ID ,Flash base,Flash size ,uniform,total sectors,border, , ,sector0 size,sector1 size + {0x22A7,0xFFC00000,0x400000 ,0 ,71 ,62 ,0,0,64*1024 ,8*1024 ,0,0,0,0,0,0}, + {0x22C9,0xFF800000,0x800000 ,0 ,135 ,126 ,0,0,64*1024 ,8*1024 ,0,0,0,0,0,0}, +//EON TOP + {0x22F6,0xFFC00000,0x400000 ,0 ,71 ,62 ,0,0,64*1024 ,8*1024 ,0,0,0,0,0,0}, +//EON UNIFORM + {0x22D7,0xFF800000,0x800000 ,1 ,128 ,0 ,0,0,64*1024 ,8*1024 ,0,0,0,0,0,0}, +//SPANSION + {0x227E,0xFF800000,0x800000 ,0 ,135 ,7 ,0,0,8*1024 ,64*1024 ,0,0,0,0,0,0}, + //********* 8 Bits NOR ***************** +//SST + {0xBFB6,0xFFFC0000,0x040000 ,1 ,64 ,0 ,0,0,4*1024 ,0 ,0,0,0,0,0,0}, +//END + {0xFFFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, +}; + +static struct spi_info SPI_FLASH_TYPE[]= +{ +#if defined(FLASH_SIZE_4M) + //ST + {0x20,0x16,0xFFC00000,0x10000,0xD8,2}, +#elif defined(FLASH_SIZE_8M) + +#endif + //ST + {0x20,0x16,0xFFC00000,0x10000,0xD8,2}, + //MX + {0xC2,0x15,0xFFE00000,0x10000,0xD8,2}, + {0xC2,0x17,0xFF800000,0x10000,0xD8,2}, + //NEXFLASH + {0xEF,0x15,0xFFE00000,0x10000,0xD8,2}, + //SST + {0xBF,0x80,0xFFF00000,0x08000,0x52,0xAF},//??device id + //ATMEL + {0x1F,0x60,0xFFFE0000,0x08000,0x52,2},//??device id + //NULL + {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}, +}; + +static void flash_work(int ,char **); +static unsigned short NOR16_id(); +static unsigned short NOR8_id(); +static int Erase_Seq16_0(unsigned long ); +static int Write_Seq16_0(unsigned long , unsigned short); +static int Erase_Seq8_0(unsigned long ); +static int Write_Seq8_0(unsigned long , unsigned short); +static short AMD16_sector_erase(short); +static short AMD8_sector_erase(short); +static short AMD_program_word(unsigned long,unsigned long,short,unsigned long); +static short AMD_program_byte(unsigned long,unsigned long,char,unsigned long); +static short flash_status(long,int,short); +static void SetMEM(long , short ); +static short ReadMEM(long); +static short check_sector(unsigned long,unsigned long,short *,short *); +static unsigned short NOR_flash_id(); +static short SPI_SUPPORT(); +static short NOR16_flash_upgrade(short,short); +static short NOR8_flash_upgrade(short,short); +static short NOR_upgrade(long,long); +static short SPI_upgrade(long,long); +static short SPI_flash_upgrade(short,short); +static short (*upgrade)(long,long); +static short (*flash_upgrade)(short,short); +static short SPI_flash_info(); +static short SPI_info(char CMD,char SST); +static short check_block(unsigned long addr,unsigned long len,short *start,short *end); +static short generic_block_erase(int block_num); +static short SST_program(unsigned long src,unsigned long dst,short data, unsigned long len); +static short generic_program(unsigned long src,unsigned long dst,short data,unsigned long len); +static short compare_data(unsigned long src,unsigned long dst,unsigned long len); + +//Release +RedBoot_cmd("flash","flash upgrade","[-s ][-d ][-l ]",flash_work); + + +static unsigned short first_sector,last_sector; +static unsigned long gImage_len,gImage_src,gImage_dest; +static struct flash_dev *dev ; +static unsigned short first_block,last_block; +static unsigned long counter=0; +static unsigned char gSpi_divid = 5 ; + + +static void flash_work(int argc,char **argv) +{ + struct option_info opts[3]; + bool memory_source; + unsigned long source_addr; + bool flash_dest; + unsigned long dest_addr; + bool image_length; + unsigned long image_len; + + init_opts(&opts[0], 's', true, OPTION_ARG_TYPE_NUM, + &source_addr, &memory_source, "memory source"); + + init_opts(&opts[1], 'd', true, OPTION_ARG_TYPE_NUM, + &dest_addr, &flash_dest, "flash destination"); + + init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, + &image_len, &image_length, "image length"); + + + if( !scan_opts(argc,argv, 1 ,opts ,3 ,0,0," ") ) + return ; + + if(! ( memory_source && flash_dest && image_length )) + { + diag_printf("\rNot enough parametersr\r\n"); + return; + } + if( dest_addr < FLASH_BASE ) + { + diag_printf("\rFlash destination error\r\n"); + return ; + } +#if 0 + if( image_len > FLASH_SIZE) + { + diag_printf("\rImage len error\r\n"); + return ; + } +#endif + if( (dest_addr + (image_len-1) ) < dest_addr ) + { + diag_printf("\rWrapper error\r\n"); + return ; + } + + //diag_printf("< %x,%x,%x>",source_addr,dest_addr,image_len); + gImage_len = image_len ; + gImage_src = source_addr; + gImage_dest = dest_addr; + + dev =(struct flash_dev *)malloc(sizeof(struct flash_dev *)); + + //Check if the CPU supports SPI + if(SPI_SUPPORT()==0) //SPI flash used + { + upgrade=&NOR_upgrade; + if(dev->data_width == 2) + flash_upgrade=&NOR16_flash_upgrade; + else + flash_upgrade=&NOR8_flash_upgrade; + } + else + { + upgrade=&SPI_upgrade; + flash_upgrade=&SPI_flash_upgrade; + + if(SPI_flash_info()) + { + diag_printf("\r\n===== This is a not-supported SPI FLASH ====== \r\n"); + goto END_SPI; + } + } + + +#if 1 + if(upgrade(dest_addr,image_len)) + diag_printf("\r\nUpgrading fail,please try again\r\n"); +#else //infinite test + { + while(1) + if(upgrade(dest_addr,image_len)) + diag_printf("\r\nUpgrading fail,please try again\r\n"); + } +#endif + goto END_PROCESS ; + +END_SPI: + CS_DISABLE; + //HAL_WRITE_UINT8(CTR_BASE,0x42); //return to memory-cycle + HAL_WRITE_UINT8(CTR_BASE,0x52); //return to memory-cycle + //DELAY(0x80000); + DELAY(0x5000); + +END_PROCESS: + free(dev); + + return; +} + +static short check_sector(unsigned long addr,unsigned long len,short *start,short *end) +{ + int i,j,k; + unsigned long temp,base; + unsigned long SectorSize[2]={ dev->R->sector0_size , dev->R->sector1_size }; + unsigned long Boundry=dev->R->sector0_size * ( dev->R->border + 1); + + + if(dev->R->uniform) //Uniform flash + { + for(i=0;i< dev->R->num_sector;i++) + { + base = FLASH_BASE; + temp = base + SectorSize[0]*i; + if( temp == addr ) + *start = i ; + + if( (temp+(SectorSize[0]-1)) >= (addr + (len-1))) + { + *end = i; + return 0; + } + } + } + else //Bottom or Top flash + { + for(i=0;i< dev->R->num_sector;i++) + { + if( i <= dev->R->border ) + { + base = FLASH_BASE; + temp = base + SectorSize[0]*i; + if( temp == addr ) + *start = i ; + + if( (temp+(SectorSize[0]-1)) >= (addr + (len-1))) + { + *end = i; + return 0; + } + } + else + { + base = FLASH_BASE + Boundry ; + temp = base + SectorSize[1]*(i- (dev->R->border+1)); + if( temp == addr ) + *start = i ; + if( i == dev->R->num_sector-1 ) + { + *end = i ; + return 0; + } + else + { + if(( temp+ SectorSize[1]) >= (addr + (len-1))) + { + *end = i; + return 0; + } + } + } + } + } + return 1; +} + +static short NOR8_flash_upgrade(short first,short last) +{ + int i,j,k; + int Loop; + unsigned char *temp = (unsigned char *)gImage_src; + unsigned long offset= (gImage_dest - FLASH_BASE ) ; + + + diag_printf("\r\nErase sector"); + + + for(i=first ; i<= last ;i++) + { + Loop = 5 ; + while(Loop -- ) + { + if(dev->erase(i)) + diag_printf("",i); + else + break; + if(! Loop ) + { + diag_printf("",i); + return 1; + } + } + } + + diag_printf("\r\nProgramming.."); + for(i=0;i< gImage_len ;i++) + { + //diag_printf("",gImage_src,gImage_dest,offset,*temp); + if(dev->write( (offset + i) ,0, *temp++, 0)) + { + diag_printf("",i); + return 1; + } + } + + diag_printf("\r\n"); + return 0; +} + +static short NOR16_flash_upgrade(short first,short last) +{ + int i,j,k; + int Loop; + unsigned short *temp = (unsigned short *)gImage_src; + unsigned long offset= (gImage_dest - FLASH_BASE )/2 ; + + diag_printf("\r\nErase sector"); + for(i=first ; i<= last ;i++) + { + Loop = 5 ; + while(Loop -- ) + { + if(dev->erase(i)) + diag_printf("",i); + else + break; + if(! Loop ) + { + diag_printf("",i); + return 1; + } + } + } + + diag_printf("\r\nProgramming.."); + for(i=0;i< ((gImage_len+1)/2) ;i++) + { + //diag_printf("",gImage_src,gImage_dest,offset,*temp); + if(dev->write( (offset + i) ,0, *temp++, 0)) + { + diag_printf("",i); + return 1; + } + } + + diag_printf("\r\n"); + return 0; +} + + + +static short NOR_upgrade(long source,long len) +{ + unsigned short i; + + //Must be reserved,otherwise EON is not OK + SetMEM(0,READ_MODE); + + if(! NOR_flash_id()) + { + diag_printf("\r\nThe flash is not supported"); + return 1; + } + //debug + //diag_printf("\r\nflash base=%x,data width=%x",dev->flash_base,dev->data_width); + + if(check_sector(source,len,&first_sector,&last_sector)) + { + diag_printf("Fail at check_sector"); + return 1; + } + else + diag_printf("\r\n[First Sector=%xh,Last Sector=%xh]\r\n",first_sector,last_sector); + + return(flash_upgrade(first_sector,last_sector)); + +} + +static unsigned short NOR16_id() +{ + int i; + unsigned short ManuID,DevID; + unsigned short id ; + + cyg_drv_isr_lock; + SetMEM(0x555*2,0xAAAA); + SetMEM(0x2AA*2,0x5555); + SetMEM(0x555*2,0x9090); + id= (ReadMEM(FLASH_BASE + 2 )); + cyg_drv_isr_unlock; + + return id; +} + +static unsigned short NOR8_id() +{ + int i; + unsigned short ManuID,DevID; + unsigned short id ; + + cyg_drv_isr_lock; + SetMEM(0x5555,0xAAAA); + SetMEM(0x2AAA,0x5555); + SetMEM(0x5555,0x9090); + cyg_drv_isr_unlock; + ManuID= (ReadMEM(FLASH_BASE)); + SetMEM(0,READ_MODE); + + cyg_drv_isr_lock; + SetMEM(0x5555,0xAAAA); + SetMEM(0x2AAA,0x5555); + SetMEM(0x5555,0x9090); + cyg_drv_isr_unlock; + DevID= (ReadMEM(FLASH_BASE+1)); + SetMEM(0,READ_MODE); + //debug + //diag_printf("ManuID=%x,DevID=%x",ManuID,DevID); + id = (ManuID << 8) | (unsigned char)DevID ; + + return id; +} + +static unsigned short NOR_flash_id() +{ + int i; + unsigned short ManuID,DevID; + unsigned short id ; + if(dev->data_width ==2) + id = NOR16_id(); + else + id = NOR8_id(); + + + //Debug + diag_printf("NOR Flash ID = %x \r\n",id); + + for(i=0; NOR_FLASH_TYPE[i].device_id != 0xFFFF; i++) + { + if( id != NOR_FLASH_TYPE[i].device_id ) + continue; + else + { + dev->R = (struct flash_info *)&NOR_FLASH_TYPE[i]; + + if(dev->data_width == 2) + { + if(dev->R->ERASE_SERIES==0) + dev->erase=&AMD16_sector_erase; + if(dev->R->WRITE_SERIES==0) + dev->write=&AMD_program_word; + + dev->erase_seq=&Erase_Seq16_0; + dev->write_seq=&Write_Seq16_0; + } + else if(dev->data_width == 1) + { + dev->erase=&AMD8_sector_erase; + dev->write=&AMD_program_byte; + + dev->erase_seq=&Erase_Seq8_0; + dev->write_seq=&Write_Seq8_0; + //?????????/ + } + + dev->flash_base=dev->R->flash_base; + return 1; + } + } + +#if defined(FLASH_SIZE_4M) + diag_printf("\r\n No match.It will try MX29LV320AT ERASE/WRITE \r\n"); +#else + diag_printf("\r\n No match.It will try MX29LV640AT ERASE/WRITE \r\n"); +#endif + dev->R = (struct flash_info *)&NOR_FLASH_TYPE[0]; + dev->erase=&AMD16_sector_erase; + dev->write=&AMD_program_word; + dev->erase_seq=&Erase_Seq16_0; + dev->write_seq=&Write_Seq16_0; + dev->flash_base=dev->R->flash_base; + + return 1; + +} + +// mode:0 erase +// 1 program +static short flash_status(long addr,int mode,short data) +{ + int i,j; + short cur,prev,toggle; + long temp; + volatile unsigned short status; + int LoopCount=0xFFFFF; + + temp = addr ; + addr +=FLASH_BASE ; + + prev=ReadMEM(addr); + do + { + cur=ReadMEM(addr); + toggle = ( (cur ^ prev) & TOGGLE_STATUS ); + prev = cur ; + + }while ( toggle && (( cur & TIMEOUT_STATUS)==0) ); + +#if 0 + if( cur & TIMEOUT_STATUS) + { + prev = ReadMEM(addr); + cur = ReadMEM(addr); + + if ( (prev ^ cur) & TOGGLE_STATUS) + { + //reset the flash + SetMEM(0,READ_MODE); + + diag_printf("",cur); + return 1; + } + } +#endif + if( mode )//Program + { + SetMEM(0,READ_MODE); //return to READ mode + + while(-- LoopCount) + { + if( ReadMEM(addr) == data) + //break; + return 0; + continue; + } + if( ! LoopCount) + { + diag_printf("",addr,ReadMEM(addr),data); + diag_printf(""); + return 1; + } + } + else //Erase ,below must be modified + { + int k1,k2; + for(k1=0;k1<0xfff;k1++) + { + for(k2=0;k2<0xfff;k2++) + { + //status = ReadMEM( FLASH_BASE + 2*temp); + status = ReadMEM( FLASH_BASE + (dev->data_width)*temp); + if( status == 0xFFFF ) + return 0; + } + //For debug + diag_printf("",status); + } + + SetMEM(0,READ_MODE); //return to READ mode + + return 1; + } + + + return 0; +} +static void SetMEM(long addr,short data) +{ + if(dev->data_width == 2) + //*( short *)(FLASH_BASE+2*addr) = data; + *( short *)(FLASH_BASE+addr) = data; + else if(dev->data_width == 1) + *( char *)(FLASH_BASE+addr) = (char)data; + +} +static short ReadMEM(long addr) +{ + if(dev->data_width ==2) + return *(short *)(addr); + else if(dev->data_width ==1) + return *(char *)addr; +} + +static int Erase_Seq8_0(unsigned long addr) +{ +#if 0 + //Unprotect the sector + cyg_drv_isr_lock; + SetMEM(0x555,0xAAAA); + SetMEM(0x2AA,0x5555); + SetMEM(0x555,0x9090); + SetMEM(addr ,0x0000); +#endif + //debug + //diag_printf("[Erase_Seq8_0]"); + + //Erase the sector + cyg_drv_isr_lock; + SetMEM(0x5555,0xAAAA); + SetMEM(0x2AAA,0x5555); + SetMEM(0x5555,0x8080); + SetMEM(0x5555,0xAAAA); + SetMEM(0x2AAA,0x5555); + SetMEM(addr ,0x3030); + cyg_drv_isr_unlock; +} + +static int Write_Seq8_0(unsigned long addr, unsigned short data) +{ + cyg_drv_isr_lock; + SetMEM(0x5555,0xAAAA); + SetMEM(0x2AAA,0X5555); + SetMEM(0x5555,0xA0A0); + SetMEM(addr, data); + cyg_drv_isr_unlock; +} + +static int Erase_Seq16_0(unsigned long addr) +{ + //Unprotect the sector + cyg_drv_isr_lock; + SetMEM(0x555*2,0xAAAA); + SetMEM(0x2AA*2,0x5555); + SetMEM(0x555*2,0x9090); + SetMEM(addr*2 ,0x0000); + //Erase the sector + SetMEM(0x555*2,0xAAAA); + SetMEM(0x2AA*2,0x5555); + SetMEM(0x555*2,0x8080); + SetMEM(0x555*2,0xAAAA); + SetMEM(0x2AA*2,0x5555); + SetMEM(addr*2 ,0x3030); + cyg_drv_isr_unlock; +} + +static int Write_Seq16_0(unsigned long addr, unsigned short data) +{ + cyg_drv_isr_lock; + SetMEM(0x555*2,0xAAAA); + SetMEM(0x2AA*2,0X5555); + SetMEM(0x555*2,0xA0A0); + SetMEM(addr*2, data); + cyg_drv_isr_unlock; +} + +static short AMD8_sector_erase(short sector) +{ + + long addr; + + if(dev->R->uniform) + addr = sector*dev->R->sector0_size; + + //debug + //diag_printf(" AMD8_sector_erase:setcor=%x,addr=%x\r\n",sector,addr); + + dev->erase_seq(addr); + + diag_printf("."); + return(flash_status(addr,0,0xFFFF)); + +} + +static short AMD16_sector_erase(short sector) +{ + long addr; + unsigned long temp = (dev->R->border + 1)*(dev->R->sector0_size/2); + if(dev->R->uniform) + addr = sector*dev->R->sector0_size / 2 ; + else + { + if(sector <= dev->R->border ) + addr = sector*dev->R->sector0_size / 2 ; + else + addr = temp +(dev->R->sector1_size/2)*(sector- dev->R->border -1); + } + //Debug + //diag_printf(" AMD16_sector_erase:temp=%x,sector=%x,border=%x,addr=%x\r\n",temp,sector,dev->R->border,addr ); + + dev->erase_seq(addr); + + diag_printf("."); + return(flash_status(addr,0,0xFFFF)); +} + +static short AMD_program_byte(unsigned long dest,unsigned long dummy0 ,char data,unsigned long dummy1) +{ + static int data_count=0; + + if( data_count++ == 0x4000 ) + { + data_count = 0; + diag_printf("."); + } + + if(data == 0xFFFF)//Skip program + return 0; + + dev->write_seq(dest,data); + + return(flash_status(dest,1,data)); + +} + +static short AMD_program_word(unsigned long dest,unsigned long dummy0 ,short data,unsigned long dummy1) +{ + static int data_count=0; + + if( data_count++ == 0x4000 ) + { + data_count = 0; + diag_printf("."); + } + + if(data == 0xFFFF)//Skip program + return 0; + + dev->write_seq(dest,data); + + //return(flash_status((dest*2),1,data)); + return(flash_status(dest*2,1,data)); +} + +#if 0 //For sample +static short XXX_program_word(long dest,short data) +{ + static int data_count=0; + + if( data_count++ == 0x4000 ) + { + data_count = 0; + diag_printf("."); + } + if(data == 0xFFFF)//Skip program + return 0; + + cyg_drv_isr_lock; + //SetMEM(0x555,0xAAAA); + //SetMEM(0x2AA,0X5555); + //SetMEM(0x555,0xA0A0); + //SetMEM(dest, data); + //cyg_drv_isr_unlock; + + return(flash_status((dest*2),1,data)); +} +#endif + +//Return value :0 ==>NOR FLASH +// 1 ==>SPI FLASH +static short SPI_SUPPORT() +{ + unsigned char temp; + unsigned long data; + unsigned long CPU_ID; + unsigned long Strap; + int i,j; + unsigned long CPU_SUPPORT_SPI[]={0x00323100,0x00561000,0x32330000,0x32350000,0}; + unsigned short DMCLK[]={133,150,166,175}; + + HAL_WRITE_UINT32(0xCF8,0x80000090); + HAL_READ_UINT32(0xCFC,CPU_ID); + + //debug + //diag_printf("[CPU ID=%x]",CPU_ID); + CPU_ID = CPU_ID & 0xFFFFF000; + for(i=0; CPU_SUPPORT_SPI[i] != 0;i++) + { + if(CPU_ID == CPU_SUPPORT_SPI[i]) + { + //Check if the bootstrap + HAL_WRITE_UINT32(0xCF8,0x80000060); + HAL_READ_UINT32(0xCFC,Strap); + //debug + //diag_printf("[Strap=%x]",Strap); +#if defined(__R3231__) || defined(__W5610__) + if(Strap & 0x00400000) + { + //j = Strap & 0x00000300 ;; + //gSpi_divid = 5; + return 1 ; + } +#else + if((Strap & 0x00030000) == 0x00030000) + { + if( (Strap & 0x0000000F) == 0 ) //Bypass mode + gSpi_divid = 1; + return 1 ; + } +#endif + else + { + //Below is 8 bits NOR + if((Strap & 0x00700000) == 0) + dev->data_width = 1; + if(Strap & 0x00200000) + dev->data_width = 2; + + return 0; + } + } + } + //For R3210 + //Below check NOR flash + HAL_WRITE_UINT32(0xCF8,0x80003840); + HAL_READ_UINT32(0xCFC,Strap); + temp = Strap & 0x00000003; + switch(temp) + { + case 0: + dev->data_width=1; + break; + case 1: + dev->data_width=2; + break; + default: + diag_printf("XXXX"); + + }; + return 0; +} + +static short SPI_flash_info() +{ + if(SPI_info(0x9F,0)) + { + if(SPI_info(0x15,0)) + { + if(SPI_info(0x90,1)) + return 1; + } + } + return 0; +} + +static short SPI_info(char CMD,char SST) +{ + unsigned char manufacture_id,memory_id,device_id; + int i; + + //set the SPI IO + HAL_WRITE_UINT32(0xCF8,0x80000040); + HAL_WRITE_UINT32(0xCFC,0xFC01); + + CS_DISABLE; + HAL_WRITE_UINT8(CTR_BASE,FIFO_ENABLE | AUTO_FETCH_DISABLE | gSpi_divid ); + + CS_ENABLE; + SPI_RDID(CMD); + SPI_CHECK_OUT; + + if(SST) + { + HAL_WRITE_UINT8(OUTPORT,0); + SPI_CHECK_OUT; + + HAL_WRITE_UINT8(OUTPORT,0); + SPI_CHECK_OUT; + + HAL_WRITE_UINT8(OUTPORT,0); + SPI_CHECK_OUT; + } + + SPI_CHECK_IN; + HAL_READ_UINT8(INPORT,manufacture_id); + + SPI_CHECK_IN; + HAL_READ_UINT8(INPORT,memory_id); + + SPI_CHECK_IN; + HAL_READ_UINT8(INPORT,device_id); + + CS_DISABLE; + + if(SST) + device_id = memory_id ; + + for(i=0;SPI_FLASH_TYPE[i].manufacture_id != 0xFF ;i++) + { + if(SPI_FLASH_TYPE[i].manufacture_id == manufacture_id ) + { + if(SPI_FLASH_TYPE[i].device_id == device_id ) + { + diag_printf("\r\nManfacture=%x,Deivce ID=%x\r\n",manufacture_id,device_id); + dev->erase=&generic_block_erase; + if(SST) + dev->write=&SST_program; + else + dev->write=&generic_program; + dev->cmd_erase=SPI_FLASH_TYPE[i].cmd_erase; + dev->cmd_write=SPI_FLASH_TYPE[i].cmd_write; + dev->flash_base=SPI_FLASH_TYPE[i].flash_base; + dev->block_size=SPI_FLASH_TYPE[i].block_size; + return 0; + } + } + } + + diag_printf("\r\nSPI Manfacture=%x,Deivce ID=%x\r\n",manufacture_id,device_id); + return 1; +} + +static short generic_program(unsigned long src,unsigned long dst,short dummy, unsigned long len) +{ + int i; + unsigned char AD1,AD2,AD3 ; + unsigned long temp_multi,offset,tmp; + unsigned char *tmp_src = (unsigned char *)src ; + unsigned long tmp_dst= dst; + + //diag_printf("\r\n[generic_program]\r\n"); + + temp_multi = len / MAX_CYCLE ; + + CS_DISABLE; + //HAL_WRITE_UINT8(CTR_BASE,0x31); //FIFO used + HAL_WRITE_UINT8(CTR_BASE,FIFO_ENABLE | AUTO_FETCH_DISABLE | gSpi_divid ); + + for(i=0 ; i < temp_multi ; i++,tmp_dst+=MAX_CYCLE) + { + int count=0 ; + + offset = tmp_dst - dev->flash_base; + //debug + //diag_printf("\r\noffset=%x,dst=%x,tmp_dst=%x,dev->flash_base=%x",offset,dst,tmp_dst,dev->flash_base); + AD1=(unsigned char)( offset & 0x000000FF ) ; + AD2=(unsigned char)(( offset & 0x0000FF00 ) >> 8); + AD3=(unsigned char)(( offset & 0x00FF0000 ) >> 16); + + //debug + //diag_printf("[AD1=%x,AD2=%x,AD3=%x,cmd=%x]",AD1,AD2,AD3,dev->cmd_write); + + SPI_WRITE(dev->cmd_write,AD1,AD2,AD3); + + while(1) + { + HAL_WRITE_UINT8(OUTPORT,*tmp_src++); + + if(( count & (FIFO_SIZE-1))==(FIFO_SIZE-1)) + { + SPI_CHECK_OUT; + + } + + if( (count & (MAX_CYCLE-1)) == (MAX_CYCLE-1) ) + { + SPI_CHECK_BUSY; + CS_DISABLE ; + break ; + } + + count ++; + } + } + + if( len % 256 ) + { + tmp = len - MAX_CYCLE * temp_multi ; + + + offset = tmp_dst - dev->flash_base; + AD1=(unsigned char)( offset & 0x000000FF ) ; + AD2=(unsigned char)(( offset & 0x0000FF00 ) >> 8); + AD3=(unsigned char)(( offset & 0x00FF0000 ) >> 16); + + SPI_WRITE(dev->cmd_write,AD1,AD2,AD3); + + for(i=0 ; i < tmp ;i++) + { + HAL_WRITE_UINT8(OUTPORT,*tmp_src++); + SPI_CHECK_OUT; + } + + CS_DISABLE; + + } +} + +static short SST_program(unsigned long src,unsigned long dst,short dummy, unsigned long len) +{ + + int i; + //unsigned char *data = *(unsigned char *)src ; + unsigned char AD1,AD2,AD3 ; + unsigned long offset; + unsigned char *tmp_src = (unsigned char *)src ; + unsigned long tmp_dst= dst; + + offset = tmp_dst - dev->flash_base; + //debug + //diag_printf("\r\noffset=%x,tmp_dst=%x,dev->flash_base=%x",offset,tmp_dst,dev->flash_base); + + AD1=(unsigned char)( offset & 0x000000FF ) ; + AD2=(unsigned char)(( offset & 0x0000FF00 ) >> 8); + AD3=(unsigned char)(( offset & 0x00FF0000 ) >> 16); + + CS_DISABLE; + //HAL_WRITE_UINT8(CTR_BASE,0x31); //FIFO used + HAL_WRITE_UINT8(CTR_BASE,FIFO_ENABLE | AUTO_FETCH_DISABLE | gSpi_divid ); + SST_AAI_START(AD1,AD2,AD3,*tmp_src++); + + + for(i =0;i <(len -1);i++) + { + CS_ENABLE + + HAL_WRITE_UINT8(OUTPORT,0xAF); + SPI_CHECK_OUT ; + + HAL_WRITE_UINT8(OUTPORT,*tmp_src++); + SPI_CHECK_OUT + + SPI_CHECK_BUSY + } + + SST_AAI_STOP; +} + +static short generic_block_erase(int block_num) +{ + char value; + unsigned char AD1,AD2,AD3; + unsigned long addr = dev->block_size * block_num ; + + AD1 =(char)( addr & 0x000000FF ); + AD2= (char)((addr & 0x0000FF00) >>8); + AD3= (char)((addr & 0x00FF0000) >>16); + + //debug + //diag_printf("AD1=%x,AD2=%x,AD3=%x",AD1,AD2,AD3); + //diag_printf("Erase_cmd=%x,SPI_DIVID=%x",dev->cmd_erase,gSpi_divid); + CS_DISABLE ; + //HAL_WRITE_UINT8(CTR_BASE, 0x34); + HAL_WRITE_UINT8(CTR_BASE,FIFO_ENABLE | AUTO_FETCH_DISABLE | gSpi_divid ); + SECTOR_ERASE(dev->cmd_erase,AD1,AD2,AD3); + + SPI_CHECK_BUSY ; +} + +static short SPI_upgrade(long source,long len) +{ + unsigned short id,i; + unsigned short match =0; + + if(check_block(source,len,&first_block,&last_block)) + { + diag_printf("X"); + return 1; + } + else + diag_printf("\r\n[First Sector=%xh,Last Sector=%xh]\r\n",first_block,last_block); + + + return(flash_upgrade(first_block,last_block)); +} + +static short SPI_flash_upgrade(short first,short last) +{ + unsigned int i,j,k; + int Loop; + unsigned long tmp_len; + unsigned long tmp_dst = gImage_dest; + unsigned long tmp_src = gImage_src; + + diag_printf("\r\n"); + for(i=first ; i<= last ;i++) + { + dev->erase(i); + diag_printf("\rFlash upgrading -"); + if( i < last ) + tmp_len = dev->block_size ; + else + tmp_len = gImage_len - (dev->block_size * ( last - first) ); + + dev->write(tmp_src,tmp_dst,0,tmp_len); + diag_printf("\rFlash upgrading |"); + if(compare_data(tmp_src,tmp_dst,tmp_len)) + { + diag_printf("\r\n Compare data fail"); + return 1; + } + //else + // diag_printf(" Compare OK\r\n"); + + tmp_dst += dev->block_size; + tmp_src += dev->block_size; + + } + + diag_printf("\r\n"); + return 0; +} + +static short check_block(unsigned long addr,unsigned long len,short *start,short *end) +{ + int i,j,k ; + unsigned long temp,base ; + + //diag_printf("\r\naddr=%x, base=%x,block_size=%x\r\n",addr,dev->flash_base,dev->block_size); + *start = (addr - dev->flash_base )/dev->block_size; + *end = *start + (len / dev->block_size) - 1 ; + //diag_printf("*start=%x,*end=%x",*start,*end); + if( len % dev->block_size ) + *end +=1 ; + return 0; +} + +static short compare_data(unsigned long src,unsigned long dst,unsigned long len) +{ + int i,j; + unsigned long *tmp_dst=(unsigned long *)dst; + unsigned long *tmp_src=(unsigned long *)src; + unsigned long tmp_len = len /4 ; + + //Use memory-cycle to check; + CS_DISABLE; + //HAL_WRITE_UINT8(CTR_BASE,0x42); + //HAL_WRITE_UINT8(CTR_BASE,0x02); + HAL_WRITE_UINT8(CTR_BASE,FIFO_ENABLE | gSpi_divid); + //DELAY(0x1000); + + for(i =0;i +#include + //----------------------------------------------------------------------------- // New Hal_Diag init to comply with the eCos/ROM Calling Interface. @@ -79,6 +81,261 @@ channel_data_t pc_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS]; +#if defined (INIT_SUPERIO) && defined(WINBOND_83627) +void Winbond83627_init() +{ + int i,j; +//Enter configure mode + HAL_WRITE_UINT8(0x2E,0x87); + HAL_WRITE_UINT8(0x2E,0x87); + +//Software reset + HAL_WRITE_UINT8(0x2E,2); + HAL_WRITE_UINT8(0x2F,1); + +#ifdef FDC_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x60); //IO + HAL_WRITE_UINT8(0x2F,3); + HAL_WRITE_UINT8(0x2E,0x62); + HAL_WRITE_UINT8(0x2E,0xF0); + + HAL_WRITE_UINT8(0x2E,0x70); //FDC INIT + HAL_WRITE_UINT8(0x2F,6); + + HAL_WRITE_UINT8(0x2E,0x74); //DMA channel + HAL_WRITE_UINT8(0x2F,2); + + HAL_WRITE_UINT8(0x2E,0xF0); + HAL_WRITE_UINT8(0x2F,8); + + HAL_WRITE_UINT8(0x2E,0xF1); //FDC option + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0xF2); //FDC type 102 + HAL_WRITE_UINT8(0x2F,0xFF); + + HAL_WRITE_UINT8(0x2E,0xF4); //FDC driver type select + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x30); //Active + HAL_WRITE_UINT8(0x2F,1); +#endif +#ifdef LPT_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,1); + + HAL_WRITE_UINT8(0x2E,0x30); //Disable LPT + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x60); //MSB IO ADDR + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x61); //LSB IO ADDR + HAL_WRITE_UINT8(0x2F,0x78); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ=7 + HAL_WRITE_UINT8(0x2F,7); + + HAL_WRITE_UINT8(0x2E,0x74); //DMA channel + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0xF0); //LPT config + HAL_WRITE_UINT8(0x2F,0x8C); + + HAL_WRITE_UINT8(0x2E,0xF1); //LPT config + HAL_WRITE_UINT8(0x2F,0xC5); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable LPT + HAL_WRITE_UINT8(0x2F,1); +#endif +#ifdef UARTA_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,2); + + HAL_WRITE_UINT8(0x2E,0x30); //Disable + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x60); //MSB IO ADDR + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x61); //LSB IO ADDR + HAL_WRITE_UINT8(0x2F,0xF8); + + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ=4 + HAL_WRITE_UINT8(0x2F,4); + + HAL_WRITE_UINT8(0x2E,0xF0); //Mode + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable UARTA + HAL_WRITE_UINT8(0x2F,1); +#endif +#ifdef KBC_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,5); + + HAL_WRITE_UINT8(0x2E,0x30); //Disable + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0xF0); //12Mhz clock + HAL_WRITE_UINT8(0x2F,0x10); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable + HAL_WRITE_UINT8(0x2F,0x1); + + HAL_WRITE_UINT8(0x2E,0x60); //KBC data port=0x0060 + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x61); + HAL_WRITE_UINT8(0x2F,0x60); + + HAL_WRITE_UINT8(0x2E,0x62); //KBC command port=0x0064 + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x63); + HAL_WRITE_UINT8(0x2F,0x64); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ + HAL_WRITE_UINT8(0x2F,1); + + HAL_WRITE_UINT8(0x2E,0x72); + HAL_WRITE_UINT8(0x2F,0x0C); +#endif +#ifdef UARTB_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x30); //Disable + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x60); //MSB IO ADDR + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x61); //LSB IO ADDR + HAL_WRITE_UINT8(0x2F,0xE8); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ=5 + HAL_WRITE_UINT8(0x2F,5); + + HAL_WRITE_UINT8(0x2E,0xF0); //Mode + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable UARTB + HAL_WRITE_UINT8(0x2F,1); +#endif + + HAL_WRITE_UINT8(0x2E,0xAA); //Leave configure mode + + + //For debug + HAL_WRITE_UINT8(0x340,0xFF); + +} +#endif +#if defined(INIT_SUPERIO) && defined(ITE_8761) +void IT8761_init() +{ + int i,j; +//Enter configure mode + HAL_WRITE_UINT8(0x2E,0x87); + HAL_WRITE_UINT8(0x2E,0x61); + HAL_WRITE_UINT8(0x2E,0x55); + HAL_WRITE_UINT8(0x2E,0x55); +#ifdef FDC_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable FDC + HAL_WRITE_UINT8(0x2F,1); + + HAL_WRITE_UINT8(0x2E,0x60); //MSB IO + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x61); //LSB IO + HAL_WRITE_UINT8(0x2F,0xF0); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ + HAL_WRITE_UINT8(0x2F,6); + + HAL_WRITE_UINT8(0x2E,0x74); //Channel + HAL_WRITE_UINT8(0x2F,0x2); + + HAL_WRITE_UINT8(0x2E,0xF0); //PC/AT mode + HAL_WRITE_UINT8(0x2F,0x0C); +#endif +#ifdef KBC_INIT + HAL_WRITE_UINT8(0x2E,0x7); //Logic device + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x30); //Disable KBC + HAL_WRITE_UINT8(0x2F,0x0); + + HAL_WRITE_UINT8(0x2E,0xF0); //12Mhz clock + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable KBC + HAL_WRITE_UINT8(0x2F,1); + + HAL_WRITE_UINT8(0x2E,0x60); //KBC data port=0x0060 + HAL_WRITE_UINT8(0x2F,0x0); + HAL_WRITE_UINT8(0x2E,0x61); + HAL_WRITE_UINT8(0x2F,0x60); + + HAL_WRITE_UINT8(0x2E,0x62); //KBC command port=0x0064 + HAL_WRITE_UINT8(0x2F,0x00); + HAL_WRITE_UINT8(0x2E,0x63); + HAL_WRITE_UINT8(0x2F,0x64); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ + HAL_WRITE_UINT8(0x2F,1); +#endif +#ifdef MOUSE_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,4); + + HAL_WRITE_UINT8(0x2E,0x30); //Enable + HAL_WRITE_UINT8(0x2F,1); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ + HAL_WRITE_UINT8(0x2F,0x0C); +#endif +#ifdef UART_INIT + HAL_WRITE_UINT8(0x2E,7); //Logic device + HAL_WRITE_UINT8(0x2F,1); + + HAL_WRITE_UINT8(0x2E,0x30); //Disable + HAL_WRITE_UINT8(0x2F,0); + + HAL_WRITE_UINT8(0x2E,0x60); //MSB IO + HAL_WRITE_UINT8(0x2F,3); + + HAL_WRITE_UINT8(0x2E,0x61); //LSB IO + HAL_WRITE_UINT8(0x2F,0xF8); + + HAL_WRITE_UINT8(0x2E,0x70); //IRQ + HAL_WRITE_UINT8(0x2F,4); + + HAL_WRITE_UINT8(0x2E,0xF0); + HAL_WRITE_UINT8(0x2F,1); + + + HAL_WRITE_UINT8(0x2E,0x30); //Enable + HAL_WRITE_UINT8(0x2F,1); +#endif + + HAL_WRITE_UINT8(0x2E,2); //Leave configure mode + HAL_WRITE_UINT8(0x2F,2); + + + //For debug + HAL_WRITE_UINT8(0x340,0xFF); +} +#endif + void cyg_hal_plf_comms_init(void) { @@ -90,6 +347,11 @@ initialized = 1; +#ifdef INIT_SUPERIO + SuperIO_INIT(); + //HAL_WRITE_UINT8(0x340,0xFF); +#endif + num_serial = CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; #ifdef CYGSEM_HAL_I386_PC_DIAG_SCREEN --num_serial; --- ecos-2.0/packages/hal/i386/pc/v2_0/src/romboot.S 2002-05-24 01:03:14.000000000 +0200 +++ ecos-2.0-rdc/packages/hal/i386/pc/v2_0/src/romboot.S 2006-08-05 16:06:16.000000000 +0200 @@ -53,19 +53,19 @@ ######DESCRIPTIONEND#### ## ##============================================================================= - + #include #include #include +#include #============================================================================== // .file "romboot.S" #------------------------------------------------------------------------------ - .code16 romboot_start: @@ -79,19 +79,224 @@ movw $0,%ax movw %ax,%es - # Call video bios to init display - movw $0xc000,%bx - movw %bx,%ds - movw 0x0000,%ax - movw $0x0000,%bx - movw %bx,%ds - cmpw $0xAA55,%ax - jne 1f - .byte 0x9a # lcall - .word 0x0003 # offset - .word 0xc000 # segment -1: + + # hlin -> + # init chipset + + movw $0x4d0,%dx # master interrupt + movb $0xf8,%al # irq5 level, others edge + outb %al,%dx + incw %dx # slave interrupt + movb $0xde,%al # irq15,14,12,11,10,9 level; others edge + outb %al,%dx + + # init DRAM refresh + movw $0x43,%dx # + movb $0x54,%al # + outb %al,%dx + movw $0x41,%dx # + movb $0x12,%al # + outb %al,%dx + + # enable L1 cache + + invd + movl %cr0,%eax + andl $0x9fffffff, %eax + movl %eax,%cr0 + + # init north bridge +#if defined(__R3210__) + movw $0xcf8,%dx + movl $0x80000068,%eax + outl %eax,%dx + movb $0xfc,%dl + movl $0x0006C99F,%eax #For CPU=150Mhz + outl %eax,%dx +#endif + + movw $0xcf8,%dx + movl $0x8000006c,%eax # memory size + outl %eax,%dx + movb $0xfc,%dl + movl $MEM_SIZE,%eax + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80000070,%eax # + outl %eax,%dx + movb $0xfc,%dl + movl $0x04000003,%eax # + outl %eax,%dx + + # delay line for Memory + movw $0xcf8,%dx + movl $0x80000064,%eax # + outl %eax,%dx + movb $0xfc,%dl + inl %dx,%eax + andl $0xff00ffff,%eax + orl $DELAY_LINE,%eax + outl %eax,%dx + +#if defined(__R32331__) || defined(__R32351__) + movw $0xcf8,%dx + movl $0x80000074,%eax # DDR Memory timing reg + outl %eax,%dx + movb $0xfc,%dl + movl $0x036B8E55,%eax # DDR II + outl %eax,%dx +#endif + movw $0xcf8,%dx # memory attribute + movl $0x80000084,%eax # + outl %eax,%dx + movb $0xfc,%dl + movl $0x00000000,%eax # 0x15500050 pc bios + outl %eax,%dx + + # init MAC0 + movw $0xcf8,%dx + movl $0x8000403c,%eax # IRQ + outl %eax,%dx + movb $0xfc,%dl + movl $0x0000000a,%eax # IRQ 10 + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80004010,%eax # IO base address + outl %eax,%dx + movb $0xfc,%dl + movl $0x0000e801,%eax # + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80004014,%eax # Memory mapped IO address + outl %eax,%dx + movb $0xfc,%dl + movl $0xd1900000,%eax # + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80004004,%eax # enable command register + outl %eax,%dx + movb $0xfc,%dl + movw $0x07,%ax # I/O, Mem, Master + outw %ax,%dx + + # init MAC1 + movw $0xcf8,%dx + movl $0x8000483c,%eax # IRQ + outl %eax,%dx + movb $0xfc,%dl + movl $0x0000000b,%eax # IRQ 11 + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80004810,%eax # IO base address + outl %eax,%dx + movb $0xfc,%dl + movl $0x0000e901,%eax # + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80004814,%eax # Memory mapped IO address + outl %eax,%dx + movb $0xfc,%dl + movl $0xd2900000,%eax # + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80004804,%eax # enable command register + outl %eax,%dx + movb $0xfc,%dl + movw $0x07,%ax # I/O, Mem, Master + outw %ax,%dx + + + # init south bridge + movw $0xcf8,%dx + movl $0x80003840,%eax # + outl %eax,%dx + movb $0xfc,%dl + inl %dx,%eax + # movl $0x80010600,%eax # enable 128K ROM + # movl $0x87ff0600,%eax # enable TSOP FLASH ROM + #orl $0x00010000,%eax + orl $0x87ff0600,%eax # enable Flash(0xffc00000 ~ 0xffffffff) and enable internal port 92 + outl %eax,%dx + + movw $0xcf8,%dx + movl $0x80003844,%eax # + outl %eax,%dx + movb $0xfc,%dl + movl $0x00000010,%eax # + outl %eax,%dx + movw $0xcf8,%dx + movl $0x80003850,%eax # + outl %eax,%dx + movb $0xfc,%dl +#ifdef INIT_SUPERIO + movl $0x82C005c1,%eax # Include super I/O COM support +#else + #movl $0x840004c1,%eax # No init LPC + movl $0x840000c1,%eax # No init LPC +#endif + outl %eax,%dx # 53h for internal UART control + + movw $0xcf8,%dx + movl $0x80003854,%eax # internal UART COM port + outl %eax,%dx + movb $0xfc,%dl +# movl $0x000002f8,%eax # RDC UART io port + movl $UART1_IO_BASE,%eax + outl %eax,%dx + + + movw $0xcf8,%dx + movl $0x8000385c,%eax # Buffer Strength + outl %eax,%dx + movb $0xfc,%dl + movl $SDRAM_DRIVING_CURRENT,%eax + outl %eax,%dx +# +# shadow F/E segment for 128K +# + movw $0xcf8,%dx # memory attribute + movl $0x80000084,%eax # + outl %eax,%dx + movb $0xfc,%dl + movl $0x2aa00000,%eax # bit 27-20 for E segment + outl %eax,%dx # bit 29-28 for F segment + # 10b: read from PCI, write to SDRAM + xorw %si,%si + xorw %di,%di + movw $0xe000,%ax + movw %ax,%ds + movw %ax,%es + cld + movw $0x4000,%cx + rep movsl + + xorw %si,%si + xorw %di,%di + movw $0xf000,%ax + movw %ax,%ds + movw %ax,%es + cld + movw $0x4000,%cx + rep movsl + + movw $0xcf8,%dx # memory attribute + movl $0x80000084,%eax # + outl %eax,%dx + movb $0xfc,%dl + movl $0x3ff00000,%eax # bit 27-20 for E segment + outl %eax,%dx # bit 29-28 for F segment + # 11b: read/write from/to SDRAM + + + movw %cs,%ax movw %ax,%ds # set ES == 0 @@ -102,7 +307,8 @@ movw $(gdtEnd - gdtStart),%ax movw %ax,%es:0 lea gdtStart,%ax - addw $0xFF00,%ax + #addw $0xFc00,%ax # hlin, for 512B code + addw $0xFB00,%ax # movw %ax,%es:2 movw $0x000F,%ax movw %ax,%es:4 @@ -180,16 +386,20 @@ # jump to start of ROM, where the PM code starts # ljmp $8,$0xF0000 .byte 0x66,0xea # opsize + ljmp opcode - .long 0x000F0000 # destination address + .long 0x000e0000 # destination address for 128K ROM +# .long 0x000F0000 # destination address for 64K ROM .word 0x0008 # code selector .code16 - .org 0xF0 + .org 0x4F0 romboot_reset: - jmp romboot_start +# jmp romboot_start + .byte 0xea # to update CS for DT to work properly + .word 0xfb00 + .word 0xf000 - .org 0x100 + .org 0x500 #------------------------------------------------------------------------------ # end of romboot.S --- ecos-2.0/packages/hal/i386/pc/v2_0/src/romboot.ld 2008-02-16 15:43:30.000000000 +0100 +++ ecos-2.0-rdc/packages/hal/i386/pc/v2_0/src/romboot.ld 2005-05-19 13:20:38.000000000 +0200 @@ -2,7 +2,7 @@ MEMORY { - rom : ORIGIN = 0x00000, LENGTH = 0x100 + rom : ORIGIN = 0x00000, LENGTH = 0x500 } SECTIONS --- ecos-2.0/packages/redboot/v2_0/src/io.c 2002-11-05 05:27:05.000000000 +0100 +++ ecos-2.0-rdc/packages/redboot/v2_0/src/io.c 2005-07-12 19:37:33.000000000 +0200 @@ -54,6 +54,8 @@ //========================================================================== #include "redboot.h" +#include +#include #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS // GDB interface functions @@ -649,3 +651,12 @@ va_start(ap, fmt); return _verify_action(timeout, fmt, ap); } + +void initial_serial() +{ + unsigned char fifo_ctr; + + HAL_READ_UINT8(UART1_IO_BASE+2 , fifo_ctr); + fifo_ctr |= 0x60; //clear the TX/RX buffer + HAL_WRITE_UINT8(UART1_IO_BASE+2, fifo_ctr); +} --- ecos-2.0/packages/redboot/v2_0/src/main.c 2003-02-04 22:42:51.000000000 +0100 +++ ecos-2.0-rdc/packages/redboot/v2_0/src/main.c 2006-08-05 23:51:32.000000000 +0200 @@ -55,6 +55,9 @@ #define DEFINE_VARS #include +#include +#include + #include #include #include @@ -128,6 +131,21 @@ extern void HAL_ARCH_PROGRAM_NEW_STACK(void *fun); #endif +void RDC_PCI_INIT(void); +void RDC_DISABLE_WDT(void); +void INIT_GPCS(void); +void INIT_SLOT3(void); +void INIT_SLOT1(void); +void INIT_SLOT2(void); +void INIT_CARDBUS(void); +#if defined(__W5610__) +void INIT_ZD1212B(void); +#endif +#if defined(__R3210__) +void INIT_ITE8212(void); +void INIT_USB(void); +void INIT_MINIPCI(void); +#endif void do_version(int argc, char *argv[]) @@ -145,6 +163,9 @@ diag_printf("RAM: %p-%p, %p-%p available\n", (void*)ram_start, (void*)ram_end, (void*)user_ram_start, (void *)user_ram_end); + diag_printf(BOOT_INFO); + diag_printf("\r\n\n"); + #ifdef CYGPKG_IO_FLASH _flash_info(); #endif @@ -185,7 +206,13 @@ int cur; struct init_tab_entry *init_entry; extern char RedBoot_version[]; - + int Counter=0; + int RUN=0; + int BREAK=0; + + //RDC + RDC_PCI_INIT(); + // Export version information CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version); @@ -282,6 +309,8 @@ } #endif + initial_serial(); //pre-clear the uart TX/RX buffer + while (true) { if (prompt) { diag_printf("RedBoot> "); @@ -290,13 +319,33 @@ #if CYGNUM_REDBOOT_CMD_LINE_EDITING != 0 cmd_history = true; // Enable history collection #endif - res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT); +// ==> hlin +#if 1 + res = _rb_gets(line, sizeof(line), CYGNUM_REDBOOT_CLI_IDLE_TIMEOUT); + + if(RUN) + { + memcpy((char *)KERNEL_RAM_BASE,(char *)KERNEL_FLASH_BASE,KERNEL_LEN); + memcpy((char *)INITRD_RAM_BASE,(char *)INITRD_FLASH_BASE,INITRD_LEN); + res = _GETS_OK ; + //strcpy( line,"linux -b 0x400000 -l 0x200000 -s 0x1e0000 -c \"console=ttyS0,38400\"" ) ; + strcpy( line, LINUX_CMD_S); + } +#endif +// <== hlin #if CYGNUM_REDBOOT_CMD_LINE_EDITING != 0 cmd_history = false; // Enable history collection #endif - if (res == _GETS_TIMEOUT) { - // No input arrived - } else { + + if (res == _GETS_CTRLC) + BREAK=1; + + if (res == _GETS_TIMEOUT) { + if(! BREAK) + if( Counter++ == BOOT_TIME ) + RUN=1; + + } else { #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS if (res == _GETS_GDB) { int dbgchan; @@ -322,8 +371,10 @@ } else #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + expand_aliases(line, sizeof(line)); command = (char *)&line; + if ((*command == '#') || (*command == '=')) { // Special cases if (*command == '=') { @@ -491,12 +542,22 @@ } #ifdef HAL_PLATFORM_RESET +void RDC_RESET() +{ + int i; + HAL_WRITE_UINT32(0xCF8,0x80003840); + HAL_READ_UINT32(0xCFC,i); + i |= 0x1600 ; + HAL_WRITE_UINT32(0xCFC,i); + HAL_WRITE_UINT8(0x92,1); +} void do_reset(int argc, char *argv[]) { diag_printf("... Resetting."); CYGACC_CALL_IF_DELAY_US(2*100000); diag_printf("\n"); + RDC_RESET(); CYGACC_CALL_IF_RESET(); diag_printf("!! oops, RESET not working on this platform\n"); } @@ -558,20 +619,6 @@ do_baud_rate(int argc, char *argv[]) { int new_rate, ret, old_rate; - bool new_rate_set; - hal_virtual_comm_table_t *__chan; - struct option_info opts[1]; -#ifdef CYGSEM_REDBOOT_FLASH_CONFIG - struct config_option opt; -#endif - - init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM, - (void **)&new_rate, (bool *)&new_rate_set, "new baud rate"); - if (!scan_opts(argc, argv, 1, opts, 1, 0, 0, "")) { - return; - } - __chan = CYGACC_CALL_IF_CONSOLE_PROCS(); - if (new_rate_set) { diag_printf("Baud rate will be changed to %d - update your settings\n", new_rate); _sleep(500); // Give serial time to flush old_rate = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_GETBAUD); @@ -624,3 +671,330 @@ bist(void) { } + +void RDC_PCI_INIT(void) +{ + int i,j ; + +#if defined(__R3210__) + #ifdef ATHEROS_WIRELESS + HAL_WRITE_UINT32(0xCF8,0x800000F8); + HAL_WRITE_UINT16(0xCF8,0x2A); + #endif + INIT_GPCS(); + + INIT_SLOT1(); + INIT_MINIPCI(); + INIT_SLOT3(); + INIT_ITE8212(); + INIT_USB(); + + + //PCI Routing + HAL_WRITE_UINT32(0xCF8,0x80003858); + HAL_WRITE_UINT32(0xCFC,0xDF9311B7); + +#elif defined(__R3231__) + INIT_GPCS(); + + INIT_SLOT1(); + INIT_SLOT2(); + INIT_SLOT3(); + + //PCI Routing + HAL_WRITE_UINT32(0xCF8,0x80003858); + HAL_WRITE_UINT32(0xCFC,0xDF9311B7); +#elif defined(__W5610__) + INIT_GPCS(); + INIT_ZD1212B(); + + + //PCI Routing + HAL_WRITE_UINT32(0xCF8,0x80003858); + HAL_WRITE_UINT32(0xCFC,0xDF9311B7); +#elif defined(__R3233__) + RDC_DISABLE_WDT(); + + INIT_SLOT1(); + INIT_SLOT2(); + INIT_SLOT3(); + INIT_CARDBUS(); + + + //PCI Routing + HAL_WRITE_UINT32(0xCF8,0x80003858); + HAL_WRITE_UINT32(0xCFC,0xDF9311B7); +#elif defined(__A9100__) + RDC_DISABLE_WDT(); + + INIT_SLOT1(); + INIT_SLOT2(); + INIT_SLOT3(); + + //PCI Routing + HAL_WRITE_UINT32(0xCF8,0x80003858); + HAL_WRITE_UINT32(0xCFC,0xDF9311B7); +#elif defined(__R3235__) + +#endif +} + +void RDC_DISABLE_WDT(void) +{ + + HAL_WRITE_UINT8(0x22,0x13); + HAL_WRITE_UINT8(0x23,0xC5); + + HAL_WRITE_UINT8(0x22,0x37); + HAL_WRITE_UINT8(0x23,0xBF); + + HAL_WRITE_UINT8(0x22,0x13); + HAL_WRITE_UINT8(0x23,0xC5); + +} + + +void INIT_GPCS(void) +{ + HAL_WRITE_UINT32(0xCF8,0x80003890); + HAL_WRITE_UINT32(0xCFC,0x200002); + + HAL_WRITE_UINT32(0xCF8,0x80003898); + HAL_WRITE_UINT32(0xCFC,0x300002); +} + + +void INIT_SLOT2(void) +{ + unsigned long base; + + HAL_WRITE_UINT32(0xCF8,0x8000103C); //IRQ 12 + HAL_WRITE_UINT8(0xCFC,0x0C); + + HAL_WRITE_UINT32(0xCF8,0x80001010); + HAL_READ_UINT32(0xCFC,base); + + + if(base & 1) //IO + { + HAL_WRITE_UINT32(0xCF8,0x80001010); + HAL_WRITE_UINT32(0xCFC,SLOT2_IO_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80001004); //IO,Master + HAL_WRITE_UINT16(0xCFC,5); + } + else + { + HAL_WRITE_UINT32(0xCF8,0x80001010); + HAL_WRITE_UINT32(0xCFC,SLOT2_MEM_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80001004); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + } + +} + +void INIT_SLOT3(void) +{ + unsigned long base; + + HAL_WRITE_UINT32(0xCF8,0x8000183C); //IRQ 9 + HAL_WRITE_UINT8(0xCFC,9); + + HAL_WRITE_UINT32(0xCF8,0x80001810); + HAL_READ_UINT32(0xCFC,base); + + if(base & 1) //IO + { + HAL_WRITE_UINT32(0xCF8,0x80001810); + HAL_WRITE_UINT32(0xCFC,SLOT3_IO_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80001804); //IO,Master + HAL_WRITE_UINT16(0xCFC,5); + } + else + { + HAL_WRITE_UINT32(0xCF8,0x80001810); + HAL_WRITE_UINT32(0xCFC,SLOT3_MEM_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80001804); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + } +} + +void INIT_SLOT1(void) +{ + unsigned long base; + + //Fun 0 + HAL_WRITE_UINT32(0xCF8,0x8000083C); //IRQ 6 + HAL_WRITE_UINT32(0xCFC,0x80000106); + + HAL_WRITE_UINT32(0xCF8,0x80000810); + HAL_READ_UINT32(0xCFC,base); + + if(base & 1) //IO + { + HAL_WRITE_UINT32(0xCF8,0x80000810); + HAL_WRITE_UINT32(0xCFC,SLOT1_IO_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80000814); + HAL_WRITE_UINT32(0xCFC,SLOT1_IO_BASE + IO_OFF); + + HAL_WRITE_UINT32(0xCF8,0x80000818); + HAL_WRITE_UINT32(0xCFC,SLOT1_IO_BASE + IO_OFF*2); + + HAL_WRITE_UINT32(0xCF8,0x8000081C); + HAL_WRITE_UINT32(0xCFC,SLOT1_IO_BASE + IO_OFF*3); + + HAL_WRITE_UINT32(0xCF8,0x80000820); + HAL_WRITE_UINT32(0xCFC,SLOT1_IO_BASE + IO_OFF*4); + + HAL_WRITE_UINT32(0xCF8,0x80000804); //IO,Master + HAL_WRITE_UINT16(0xCFC,5); + } + else + { + //Fun 0 + HAL_WRITE_UINT32(0xCF8,0x80000810); //MEM Base + HAL_WRITE_UINT32(0xCFC,SLOT1_MEM_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80000804); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + + //Fun 1 + HAL_WRITE_UINT32(0xCF8,0x8000093C); //IRQ 12 + HAL_WRITE_UINT32(0xCFC,0x8000020C); + + HAL_WRITE_UINT32(0xCF8,0x80000910); //MEM Base + HAL_WRITE_UINT32(0xCFC,SLOT1_MEM_BASE + MEM_OFF); + + HAL_WRITE_UINT32(0xCF8,0x80000904); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + + //Fun 2 + HAL_WRITE_UINT32(0xCF8,0x80000A3C); //IRQ 9 + HAL_WRITE_UINT32(0xCFC,0x80000309); + + HAL_WRITE_UINT32(0xCF8,0x80000A10); //MEM Base + HAL_WRITE_UINT32(0xCFC,SLOT1_MEM_BASE + MEM_OFF*2); + + HAL_WRITE_UINT32(0xCF8,0x80000A04); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + } +} + +void INIT_CARDBUS() +{ + //Dev 31 + HAL_WRITE_UINT32(0xCF8,0x8000F83C); //IRQ C + HAL_WRITE_UINT8(0xCFC,12); + + HAL_WRITE_UINT32(0xCF8,0x8000F810); //MEM Base + HAL_WRITE_UINT32(0xCFC,CARDBUS_MEM_BASE ); + + HAL_WRITE_UINT32(0xCF8,0x8000F804); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + + //Configure Cardbus MEM base + HAL_WRITE_UINT32(0xCF8,0x800000B0); + HAL_WRITE_UINT32(0xCFC,CARDBUS_MEM_BASE | 1); + + //Configure Cardbus MEM mask(1000h) + HAL_WRITE_UINT32(0xCF8,0x800000B4); + HAL_WRITE_UINT32(0xCFC,0xFFFF0000); + + //Configure Cardbus IO base/mask + HAL_WRITE_UINT32(0xCF8,0x800000B8); + HAL_WRITE_UINT32(0xCFC,0xFF000000 | CARDBUS_IO_BASE | 1); +} + + +#if defined(__W5610__) +void INIT_ZD1212B(void) +{ + //4th slot + HAL_WRITE_UINT32(0xCF8,0x8000203C); //IRQ 9 + HAL_WRITE_UINT8(0xCFC,9); + + HAL_WRITE_UINT32(0xCF8,0x80002010); //MEM + HAL_WRITE_UINT32(0xCFC,SLOT4_MEM_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80002004); //MEM ,Master + HAL_WRITE_UINT16(0xCFC,6); +} +#endif + +#if defined(__R3210__) +void INIT_MINIPCI(void) +{ + //Dev 2 + HAL_WRITE_UINT32(0xCF8,0x8000103C); //IRQ 12 + HAL_WRITE_UINT16(0xCFC,0x0000010C); + + HAL_WRITE_UINT32(0xCF8,0x80001010); //MEM BASE + HAL_WRITE_UINT32(0xCFC,SLOT2_MEM_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80001004); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); +} + +void INIT_ITE8212(void) +{ + //4th slot + HAL_WRITE_UINT32(0xCF8,0x8000203C); //IRQ 9 + HAL_WRITE_UINT8(0xCFC,9); + + HAL_WRITE_UINT32(0xCF8,0x80002010); //Primary master + HAL_WRITE_UINT32(0xCFC,SLOT4_IO_BASE); + + HAL_WRITE_UINT32(0xCF8,0x80002014); //Primary slave + HAL_WRITE_UINT32(0xCFC,SLOT4_IO_BASE + IO_OFF*1); + + HAL_WRITE_UINT32(0xCF8,0x80002018); //Secondary master + HAL_WRITE_UINT32(0xCFC,SLOT4_IO_BASE + IO_OFF*2); + + HAL_WRITE_UINT32(0xCF8,0x8000201C); //Primary slave + HAL_WRITE_UINT32(0xCFC,SLOT4_IO_BASE + IO_OFF*3); + + HAL_WRITE_UINT32(0xCF8,0x80002020); //IDE Card + HAL_WRITE_UINT32(0xCFC,SLOT4_IO_BASE + IO_OFF*4); + + HAL_WRITE_UINT32(0xCF8,0x80002004); //IO,Master + HAL_WRITE_UINT16(0xCFC,5); +} + +void INIT_USB(void) +{ + //INIT EHCI + HAL_WRITE_UINT32(0xCF8,0x8000513C); //IRQ 14 + HAL_WRITE_UINT32(0xCFC,0x0000020E); + + HAL_WRITE_UINT32(0xCF8,0x80005110); //MEM BASE + HAL_WRITE_UINT32(0xCFC,IPCI_MEM_BASE0); + + HAL_WRITE_UINT32(0xCF8,0x8000510C); //Latency timer + HAL_WRITE_UINT32(0xCFC,0x00002008); + + HAL_WRITE_UINT32(0xCF8,0x80005104); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + + //INIT OHCI + HAL_WRITE_UINT32(0xCF8,0x8000503C); //IRQ 15 + HAL_WRITE_UINT32(0xCFC,0x5000010F); + + HAL_WRITE_UINT32(0xCF8,0x80005010); //MEM BASE + HAL_WRITE_UINT32(0xCFC,IPCI_MEM_BASE0 + MEM_OFF); + + HAL_WRITE_UINT32(0xCF8,0x8000500C); //Latency timer + HAL_WRITE_UINT32(0xCFC,0x00002008); + + HAL_WRITE_UINT32(0xCF8,0x80005004); //MEM,Master + HAL_WRITE_UINT16(0xCFC,6); + + //USB PHY + HAL_WRITE_UINT32(0xCF8,0x800000C0); + HAL_WRITE_UINT32(0xCFC,0x000C0000); +} + +#endif