#ifndef __R8610__H__
#define __R8610__H__

/* Project define */
	#define __R3210__
	//#define __W5610__
	//#define __R3231__
	//#define __R3233__
	//#define __A9100__
	//#define __R3235__
//======================================================================================

#define UPGRADE_BY_MAC1    		 /*marked it means it is used by MAC0  */
//#define INIT_SUPERIO                   /*marked it means system does not init super io*/
	#ifdef  INIT_SUPERIO
      		//#define   WINBOND_83627
     		  #define   ITE_8761  

      		#if defined(WINBOND_83627)
        		#define SuperIO_INIT   Winbond83627_init
        		//#define FDC_INIT		
			#define UARTA_INIT        
			//#define UARTB_INIT	  
			//#define LPT_INIT          
			//#define KBC_INIT	  
      		#elif defined(ITE_8761)
        		#define SuperIO_INIT   IT8761_init
        		//#define FDC_INIT		
			#define UART_INIT        
			//#define KBC_INIT	  
        		//#define MOUSE_INIT
      		#endif
	#endif

#define UART1_IO_BASE      0x03F8
#define UART2_IO_BASE      0x02F8

#define BOOT_LEN           0x20000
#define BOOT_TIME 	   0xFF         /* the time to wait 'CTRL+C' to press */

#define MEM_OFF		   0x1000
#define SLOT1_MEM_BASE	   0xD0010000
#define SLOT2_MEM_BASE	   0xD0020000
#define SLOT3_MEM_BASE	   0xD0030000
#define SLOT4_MEM_BASE	   0xD0040000
#define SLOT5_MEM_BASE	   0xD0050000
#define SLOT6_MEM_BASE	   0xD0060000
#define IPCI_MEM_BASE0	   0xC1000000
#define IPCI_MEM_BASE1	   0xC1010000
#define CARDBUS_MEM_BASE   0xC2000000
#define IO_OFF		   0x100
#define SLOT1_IO_BASE	   0x1001
#define SLOT2_IO_BASE	   0x2001
#define SLOT3_IO_BASE	   0x3001
#define SLOT4_IO_BASE	   0x4001
#define CARDBUS_IO_BASE	   0xC000

//=========================R3210=================================================
#if defined(__R3210__)
//#define MINI_PCI_SLOT1                 /*marked it means it is used by SLOT2 */
//#define ATHEROS_WIRELESS               /*marked it means there is no atheros wireless*/
	#define FLASH_SIZE_4M	     
	//#define FLASH_SIZE_8M
	
	#define SDRAM_SIZE_32M
	//#define SDRAM_SIZE_64M
	
	/*  MEM SIZE */
	#define MEM_EVB_16M   0x00000331   /* -6 for 166MHZ */
	#define MEM_EVB_32M   0x00000451
	#define MEM_EVB_64M   0x00000551
	#define MEM_FPGA_64M  0x00000532
	#define MEM_SIZE      MEM_EVB_64M

	/*  DELAY LINE */
	#define DELAY_LINE_EVB_32M  0x009C0000
	#define DELAY_LINE_EVB_64M  0x00770000
	#define DELAY_LINE	    DELAY_LINE_EVB_64M

	//#define SDRAM_DRIVING_CURRENT 0x00002755


        #define BOOT_INFO	  "Redboot for MGB100 by laxan\r\r\n"
//=========================R3231=================================================
#elif defined(__R3231__)

	#define FLASH_SIZE_4M	     
	
	#define SDRAM_SIZE_64M	     
	
	/*  MEM SIZE */	
	#define MEM_EVB_64M   0x00000551
	#define MEM_SIZE      MEM_EVB_64M

	/*  DELAY LINE */
	#define DELAY_LINE_EVB_64M_133  0x00770000
	#define DELAY_LINE_EVB_64M_150  0x00C80000
	#define DELAY_LINE	    	DELAY_LINE_EVB_64M_150

	//#define SDRAM_DRIVING_CURRENT 0x00002EEE

        #define BOOT_INFO	   "R3231   00:0011 08-04-2006\r\r\n"
//=========================W5610=================================================
#elif defined(__W5610__)
	#define FLASH_SIZE_4M	     
	//#define FLASH_SIZE_8M
	
	#define SDRAM_SIZE_32M
	//#define SDRAM_SIZE_64M	     
	
	
	/*  MEM SIZE */
	#define MEM_EVB_16M   0x00000331   /* -6 for 166MHZ */
	#define MEM_EVB_32M   0x00000451
	#define MEM_EVB_64M   0x00000551
	#define MEM_FPGA_64M  0x00000532
	#define MEM_SIZE      MEM_EVB_32M

	/*  DELAY LINE */
	#define DELAY_LINE_EVB_32M  0x00780000
	#define DELAY_LINE	    DELAY_LINE_EVB_32M

	//#define SDRAM_DRIVING_CURRENT 0x00002755

        #define BOOT_INFO	   "W5610   00:0011 08-04-2006\r\r\n"
        
//=========================R3233=================================================        
#elif defined(__R3233__)	
	#define FLASH_SIZE_4M	     
	//#define FLASH_SIZE_8M
	
	//#define SDRAM_SIZE_32M	
	//#define SDRAM_SIZE_64M	
	#define SDRAM_SIZE_128M     
			
	/*  MEM SIZE */	
	#define MEM_FPGA_SDRAM_64M  0x00002552
	#define MEM_FPGA_SDRAM_128M 0x00000652
	#define MEM_FPGA_DDRII_128M   0x00000672
	#define MEM_SIZE      	    MEM_FPGA_SDRAM_128M
	//#define MEM_SIZE	    MEM_FPGA_DDRII_128M

	/*  DELAY LINE */
	#define DELAY_LINE_EVB_32M  0x00780000
	#define DELAY_LINE	    DELAY_LINE_EVB_32M

	//#define SDRAM_DRIVING_CURRENT 0x00002755
	//#define SDRAM_DRIVING_CURRENT 0x00002EEE

        #define BOOT_INFO	   "R3233   00:0011 08-04-2006\r\r\n"
//=========================A9100=================================================        
#elif defined(__A9100__)	
//=========================R3235=================================================        
#elif defined(__R3235__)	        
#endif

	
#if defined(FLASH_SIZE_4M)
  	#define FLASH_BASE         0xFFC00000
  	#define INITRD_LEN         0x280000	
  	#define FLASH_SIZE         0x0400000
  	#if defined(SDRAM_SIZE_32M)
  		//Please change INITRD_RAM_BASE, if you change INITRD_LEN
    		#define INITRD_RAM_BASE       	0x1D60000	 
    		#define SDRAM_SIZE            	0x2000000  	
        	#define SDRAM_DRIVING_CURRENT 	0x00002755
  	#elif defined(SDRAM_SIZE_64M)
  		//Please change INITRD_RAM_BASE, if you change INITRD_LEN
    		#define INITRD_RAM_BASE    	0x3D60000	
    		#define SDRAM_SIZE         	0x4000000
  	        #define SDRAM_DRIVING_CURRENT 	0x00002EEE
	#elif defined(SDRAM_SIZE_128M)  
    		#define INITRD_RAM_BASE    	0x7D60000	
		#define SDRAM_SIZE         	0x8000000	
	        #define SDRAM_DRIVING_CURRENT 	0x00002EEE
  	#endif
//  	#define LINUX_CMD_S	"linux -b 0x400000 -l 0x100000 -r 0x1d60000 -s 0x280000 -c \"console=ttyS0,38400 root=/dev/mtdblock2 rootfstype=squashfs ro\""
  	#define LINUX_CMD_S     "linux -b 0x400000 -l 0x100000 -r 0x1d60000 -s 0x280000 -c \"console=ttyS0,38400 root=/dev/ram0 rw\""
#elif defined(FLASH_SIZE_8M)
  	#define FLASH_BASE         		0xFF800000
  	#define INITRD_LEN         		0x5E0000  
  	#define FLASH_SIZE         		0x0800000
  	#if defined(SDRAM_SIZE_32M)
  		//Please change INITRD_RAM_BASE, if you change INITRD_LEN
    		#define INITRD_RAM_BASE    	0x1A00000	
    		#define SDRAM_SIZE         	0x2000000
	        #define SDRAM_DRIVING_CURRENT 	0x00002755
  	#elif defined(SDRAM_SIZE_64M)
  		//Please change INITRD_RAM_BASE, if you change INITRD_LEN
    		#define INITRD_RAM_BASE    	0x3A00000	
    		#define SDRAM_SIZE         	0x4000000
	        #define SDRAM_DRIVING_CURRENT 	0x00002EEE
  	#endif  //#if defined(SDRAM_SIZE_32M)
  	#define LINUX_CMD_S	   "linux -b 0x400000 -l 0x200000 -s 0x5E0000 -c \"console=ttyS0,38400\""
#endif //#if defined(FLASH_SIZE_4M)

	#define KERNEL_FLASH_BASE  FLASH_BASE
	#define FLASH_BOOT_BASE    0xFFFE0000

	#define INITRD_FLASH_BASE  FLASH_BASE + KERNEL_LEN
	
	//if you change this value, please update LINUX_CMD_S
	/* linux kernel ram base */
	#define KERNEL_RAM_BASE    0x400000	

	//if you change this value, please update LINUX_CMD_S
	/* linux kernel size */
	#define KERNEL_LEN         0x100000	
	



#if 0 //For reference
==============================================================================================
/* Note: -b specify KERNEL_RAM_BASE
 *       -l specify KERNEL_LEN
 *       -s specify INITRD_LEN
 * if you modify above constant -- Please modify following value for your need */

#define LINUX_CMD_S	   "linux -b 0x400000 -l 0x200000 -s 0x1E0000 -c \"console=ttyS0,38400\""

==============================================================================================
/* generate rule : (ramdisk ram base) 
 * total memory size -  redboot size - INITRD_LEN 
 * ex. 0x2000000 -0x20000 - 0x260000 = 0x1D80000
 * */
#define INITRD_RAM_BASE    0x1E00000	/* Please change this value, if you change INITRD_LEN */
#endif


#endif

